6/18/2023 0 Comments Taptempo icIn the write mode, the dividing function is enabled, resulting in a 250Hz count clock. However, when the X2 switch is closed, the read mode disables IC1b so the full 500Hz clock is presented to the BCD counter by IC3d. Each pulse is indicated by LED D1 which is driven for a very short time at a reasonably low current to retain the low current consumption feature that the CMOS circuitry naturally provides.ĭuring normal operation, IC1b divides the main clock frequency by two, so that the BCD counter is in fact clocked at 250Hz. By linking R10 to pin P, positive going pulses are available, whereas linking R10 to pin N produces an output with a positive voltage pulsing to 0v. The preset cycle pulses on the outputs of IC2b are used to provide the Tap-Tempo's trigger output. The components associated with IC1a ensure that all switch bounce problems are eliminated. The stored count, and thus the count down time is proportional to the time between taps. This process repeats continuously while the unit is in the read mode. IC2b will remain set for one clock cycle, during which time IC4 and 5 are preset with the contents of the register again. When zero is reached, IC5 pin 7 goes low, causing IC2b to become reset on the next clock cycle. The BCD counter is now preset with the contents of the register, from which it counts down to zero at the 500Hz clock rate. When SW1 is tapped a second time, IC1a is knocked back into the read mode, and the accumulated count in IC4 and 5 is latched into the 8 bit register formed by IC6 and 7. IC4 and 5 comprise a four decade BCD counter, which now counts up at a rate determined by the 500Hz clock. When the tap switch SW1 is first closed, IC1a becomes set, and the write mode is selected. When the unit is switched on, C2 and R4 set IC2a, which resets IC1a via C5, causing the read mode to be selected. Tap Tempo has two modes: write mode when flip-flop IC1a is set, and read mode when IC1a is reset. IC3a, b&c form a 500Hz clock which uses three gate elements rather than the more common two, for improved stability. The full circuit diagram for the Tap-Tempo is shown in Figure 1. (Click image for higher resolution version)
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